1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to methods of manufacture thereof.
2. Description of Related Art
Referring to FIG. 10, a sectional view of a prior art device 10A is shown with a P- semiconductor substrate 11 having a buried N+ region 12A formed therein immediately next to an N+ drain region 12B. Although buried N+ region 12A and N+ drain regions 12B are ion implanted at different times, those regions are in electrical contact. A channel region CH in substrate 11 is defined between buried N+ region 12A and a source N+ region 12C, which is to the left of channel region CH in substrate 11. The N+ source region 12C is doped to the same degree as N+ drain region 12B. Above most of the substrate 11 is a gate oxide layer 21, except that above buried N+ region 12A is a tunnel oxide region 22.
Polysilicon 1 floating gate P1 is formed over the gate oxide layer 21 and the tunnel oxide region 22 extending down into the pocket left in gate oxide layer 21 by thin tunnel oxide region 22. Formed over entire device 10A, described above, including gate oxide layer 21 and floating gate P1 is interpolysilicon (silicon dioxide or ONO) dielectric layer 14 upon which is formed a polysilicon 2 control gate structure P2 extending across the entire device 10A.
Polysilicon 2 structure P2, which serves as a control gate, is coupled through capacitor C.sub.1 to the polysilicon 1 floating gate P1, which is coupled in turn by capacitors C.sub.2, C.sub.3 and C.sub.4 to the source region 12C, channel region CH, and BN+ region 12A. Capacitor C.sub.2 is connected to the source region (S) 12C, capacitor C.sub.3 is connected to the channel region CH, and capacitor C.sub.4 is connected to buried N+ region 12A which is directly connected to the drain region (D) 12B.